The present invention relates to a semiconductor integrated circuit (semiconductor device) including electrically erasable and programmable non-volatile memory elements; and, more particularly, the invention relates to a technology which can be effectively applied to, for example, a microcomputer or a memory LSI in which non-volatile memory elements, which are capable of being mounted without adding a new process to an existing CMOS process and are formed using a single layer poly flash technology, are used for a fault recovery and the like.
A single layer poly flash technology constituting the memory cell of a non-volatile memory by a single layer poly silicon gate is disclosed in Japanese Patent Laid-Open No. 334190/1994 (which corresponds to U.S. Pat. No. 5,465,231), U.S. Pat. No. 5,440,159, U.S. Pat. No. 5,504,706, Japanese Patent Laid-Open No. 212-471/1992 (which corresponds to U.S. Pat. Nos. 5,457,335, 5,767,544 and 6,064,606), and xe2x80x9cA Single Poly EEPROM Cell Structure for Use in Standard CMOS Processesxe2x80x9d, IEEE Journal of Solid State Circuits, VOL. 29, NO., 3, March 1994, pp. 311-316. For example, in a non-volatile memory cell formed by a single layer poly flash technology disclosed in Japanese Patent Laid-Open No. 334190/1994, a first conductivity type MOS transistor is formed on a semiconductor substrate and a plate electrode is formed in a second conductivity type well via an insulating layer, wherein the gate electrode of the MOS transistor and the plate electrode are connected to each other and function as a floating gate, and wherein the second conductivity type well functions as a control gate.
In Japanese Patent Laid-Open No. 212471/1992, there is also disclosed a technology for utilizing an electrically programmable non-volatile memory (EPROM) as a recovery circuit of a read only memory (ROM). Further, it is described in this publication that a non-volatile memory element having a first layer gate structure can also be used as an electrically programmable and erasable non-volatile memory element, in which a write operation is performed by hot carriers and an erase operation is performed by a tunnel current produced by applying a high voltage to a source or a drain, or the write and erase operations are performed by the tunnel current.
On the other hand, a technology for differentially utilizing two non-volatile memory elements from the viewpoint of preventing a malfunction is disclosed in Japanese Patent Laid-Open No. 163797/1992, Japanese Patent Laid-Open No. 263999/1989, Japanese Patent Laid-open No. 74392/1992, Japanese Patent Laid-Open No. 127478/1990, Japanese Patent Laid-Open No. 129091/1992, Japanese Patent Laid-Open No. 268180/1994, and U.S. Pat. No. 5,029,131. In a differential type memory cell structure, one non-volatile memory element is set in a writing state and the other non-volatile memory element is set in an erasing state, and signals read out in parallel from both the non-volatile memory elements are differentially amplified and the logic value of memory information is judged according to which output of the non-volatile memory elements in the writing state or in the erasing state becomes either an input to an inversion side or a non-inversion side.
The present inventor has studied a differential type non-volatile memory cell structure and found the following points. That is, the present inventor has found that, even in the differential type non-volatile memory cell structure, there a problem in that the rate of occurrence of faulty reading caused by degradation in a charge holding characteristic is largely affected by a threshold voltage at the initial state where a floating gate has no charge, a threshold voltage in a writing state or in an erasing state, and the state of a word line electric potential when a read operation is performed. FIG. 49 and FIG. 50, which will be hereinafter described, are not drawings showing publicly known technologies, but are drawings made by the present inventor for the purpose of facilitating an understanding of the present invention.
FIG. 49 illustrates the threshold voltage distribution of a memory cell in the case where an initial threshold voltage (Vthi) is set at a relatively high value. For example, the initial threshold voltage (Vthi) is set at a value higher than the mean value of a low threshold voltage (VthL) in an erasing state and a high threshold voltage (VthH) in a writing state. The initial threshold voltage (Vthi) is a threshold voltage in a state of thermal equilibrium. A read word line electric potential (Vread) is set in the middle region between the low threshold voltage (VthL) and the initial threshold voltage (Vthi). In this case, the voltage difference between the high threshold voltage (VthH) and the initial threshold voltage (Vthi) is small, that is, the amount of accumulated charges is small, and the self-electric field intensity applied to a gate oxide film is also small. As a result, a decrease in the threshold voltage caused by the leak of charges from the floating gate, that is, data retention, resists occurring. On the other hand, an electric field in the direction in which electrons are injected into the floating gate is applied to the tunnel oxide film of the memory cell at the low threshold voltage (VthL) by the word line voltage, when the read operation is performed, to also generate weak hot electrons near a drain to thereby generate a charge gain, which increases the threshold voltage. Since this undesirable increase in the limit of the threshold voltage reaches the initial threshold voltage (Vthi), when the threshold voltage is higher than the read word electric potential (Vread), the data is inverted and can not be read out. Therefore, the fact that the characteristic shown in FIG. 49 is comparatively strong for the data retention, but is weak for the charge gain has been made clear by the present inventor.
In contrast to this, FIG. 50 illustrates the threshold voltage distribution of the memory cell in the case where the initial threshold voltage (Vthi) is set at a relatively low value. For example, the initial threshold voltage (Vthi) is set at a value lower than the mean value of the low threshold voltage (VthL) and the high threshold voltage (VthH). The read word line electric potential (Vread) is set in the middle region between the high threshold voltage (VthH) and the initial threshold voltage (Vthi). In this case, the voltage difference between the low threshold voltage (VthL) and the initial threshold voltage (Vthi) is small, and, hence, the charge gain caused by the word line voltage when the read operation is performed resists occurring on the other hand, since a memory cell having the high threshold voltage (VthH) has a large voltage difference with respect to the initial threshold voltage (Vthi), it has a large amount of accumulated charges and high self-electric field intensity applied to the gate oxide film. As a result, an undesirable decrease in the threshold voltage easily arises from the leak of charges from the floating gate. Since this undesirable decrease in the limit of the threshold voltage reaches the initial threshold voltage (Vthi), when the threshold voltage is lower than the read word line electric potential (Vread), the data is inverted and can not be read out. Since the characteristic shown in FIG. 50 is comparatively strong for the charge gain and the difference between the low threshold voltage (VthL) and the read word line electric potential (Vread) is large, the fact that it can produce a comparatively large read current, but is weak for the data retention has been found by the present inventor.
In this manner, the high threshold voltage (VthH) of the non-volatile memory element is caused to gradually approach the initial threshold voltage (Vthi) in the state of thermal equilibrium by the leak of charges (data retention) by the self-electric field applied to the gate oxide film, and the low threshold voltage (VthL) is caused to gradually approach the initial threshold voltage (Vthi) in the state of thermal equilibrium by the electric field in the direction of the charge gain by the word line voltage (Vread) when the read operation is performed, or by the drain current. It has been recognized by the present inventor that it is difficult to maintain a high reliability of continuous reading for a long time, such as more than 10 years, because of the degradation in characteristics of both the data retention and the charge gain, even if the differential type memory cell structure is employed.
One object of the present invention is to provide a semiconductor integrated circuit which is capable of improving the long-term data holding performance by memory cells employing non-volatile memory elements.
Another object of the present invention is to provide a semiconductor integrated circuit which is mounted with non-volatile memories and is capable of remarkably reducing the rate of occurrence of faulty reading without adding any absolutely new process to an ordinary logic circuit process, a general-purpose DRAM process, or the like.
Still another object of the present invention is to provide a technology utilizing a flash memory cell constituted by a single layer polysilicon gate as a recovery circuit of a memory module or a memory circuit formed in the a semiconductor device.
The above-mentioned and other objects and new features of the present invention will be clear from the description in the present specification and from the accompanying drawings.
A general outline of typical aspects and features of the inventions disclosed in this application will be described as follows.
The present invention employs a memory cell structure which can eliminate the need for causing a channel current to flow through a non-volatile memory element in a read operation and the need for applying a large word line voltage to thereby prevent a data inversion caused by a charge gain and the like.
(1) A semiconductor integrated circuit in accordance with the present invention has a non-volatile memory element, including a first source electrode, a first drain electrode, a floating gate electrode and a control gate electrode, and is capable of having different threshold voltages; and a read transistor element, including a second source electrode, a second drain electrode and the floating gate electrode as a gate electrode, and is capable of having different mutual conductances according to the threshold voltage of the non-volatile memory element, as a basic constitution which a memory cell or an information memory cell has. A signal generated according to the mutual conductance of the read transistor element is transmitted to transmission means.
The function of the read transistor element is not limited to the above first aspect in accordance with the present invention, but it can be also grasped by the second aspect that the read transistor element includes a second source electrode, a second drain electrode and the above-mentioned floating gate electrode as a gate electrode, and is capable of having different switching states according to the threshold voltage which the non-volatile memory element has, or by the third aspect that the read transistor element includes a second source electrode, a second drain electrode and the above-mentioned floating gate electrode as a gate electrode, and is capable of having different threshold voltages according to the threshold voltage which the non-volatile memory element has.
In the above description, assume that, for example, when one threshold voltage of the non-volatile memory cell is a relatively high threshold voltage (threshold voltage in a writing state where electrons are injected into the floating gate) and the other threshold voltage is a low threshold voltage (threshold voltage in an erasing state where electrons are emitted from the floating gate), the transistor element is cut off in the state of the high threshold voltage and is on in the state of the low threshold voltage (naturally, the transistor element may be in a reverse state depending on the conductivity type of the transistor element). The erasing state of the non-volatile memory cell can be accomplished, for example, by disposing the first drain electrode and the control gate electrode of the non-volatile memory element at 0 volt like the ground voltage of a circuit and the first source electrode of the non-volatile memory element at 6 volts, and by ejecting electrons from the floating gate electrode to the first source electrode by a tunnel current. The writing state can be accomplished, for example, by disposing the first drain electrode and the control gate electrode of the non-volatile memory element at 5 volts and the first source electrode of the non-volatile memory element at 0 volt like the ground voltage of the circuit and by injecting hot electrons generated in the first drain electrode into the floating gate electrode.
Since the floating gate electrode of the non-volatile memory element is the gate electrode of the above-mentioned read transistor element, the read transistor element is set in a switching state or a mutual conductance according to the electron injection state, or the electron ejection state, in other words, the writing state or the erasing state of the floating gate electrode. Therefore, even if a select level is not applied to the control gate electrode, a current according to the switching state or the mutual conductance can flow to the transmission means (transmission circuit). A circuit diagram based on this example is shown in FIG. 1. In this circuit, a select level is not applied to the control gate electrode and hence it is recommended that a depression type MIS transistor be employed as the above-mentioned read transistor element in the sense of ensuring an amount of signal necessary for the transmission means.
On the other hand, when an enhancement type MIS transistor is employed as the above-mentioned read transistor element, it is desirable in the sense of ensuring an amount of signal necessary for the transmission means that a select level be applied to the control gate electrode also in the read operation. A circuit form based on this example is shown in a memory section in FIG. 44. It should be understood that, in this form, the read transistor element has different threshold voltages according to the electron injection state or the electron ejection state, in other words, the writing state or the erasing state of the floating gate electrode.
As described above, in the read operation, it is not necessary for a channel current to flow according to the threshold voltage of the non-volatile memory element. Accordingly, in the read operation, the source electrode and the drain electrode of the non-volatile memory element may be disposed at 0 volt like the ground potential of the circuit. Therefore, weak hot electrons are not injected into the floating gate electrode from the first drain electrode. Here, if the control gate electrode is also disposed at the ground potential of the circuit, a tunnel current is not generated, either. Granting that a select level is applied to the control gate electrode, the tunnel current is not generated between the first drain electrode and the floating gate electrode. Although a weak tunnel current or the like might be generated between the second drain electrode of the read transistor element and the floating gate electrode, if the select level of the control gate electrode is low, it can be concluded that a problem is not substantially presented. Alternatively, in the case where a drain voltage is applied to the read transistor element via MIS transistors vertically staked, as shown in FIG. 44, the drain voltage itself is lowered, and, hence, it can be concluded that a problem is not substantially presented.
In this manner, a problem of data inversion caused by the charge gain is not presented in the read operation. This can improve the data holding performance and reduce the rate of faulty reading.
(2) A constitution may be adopted in which the non-volatile memory element includes a capacitor element, having a capacitor electrode on a first semiconductor region functioning as a control gate electrode via an insulating layer and a MIS transistor including a source electrode, a drain electrode and a gate electrode, which are formed on a second semiconductor region, wherein the capacitor electrode is connected to the gate electrode and functions as a floating gate electrode.
From another aspect of the present invention, the non-volatile memory element may be composed of a first conductivity type first well region formed on a semiconductor substrate; a second conductivity type second well region formed on the semiconductor substrate; a second conductivity type first source electrode region, which is formed on the first well region and is to be connected to a first signal line; a second conductivity type first drain electrode region, which is formed on the first well region and is to be connected to a second signal line; a first insulating film formed on the principal surface of the first well region at the position between the first source electrode region and the first drain electrode region; a second insulating film formed on the principal surface of the second well region; a floating gate electrode region formed on the first and second insulating films; and a control gate electrode region, which is formed on the second well region and is to be connected to a third signal line.
In any case, a semiconductor integrated circuit including non-volatile memory elements can be fabricated without adding any absolutely new process to an ordinary logic circuit process or a general-purpose DRAM process, such as a CMOS process, a single layer polysilicon gate process, or the like.
(3) In order to reduce the rate of faulty reading by further taking data retention measures with respect to an information memory cell to which measures have been taken against the charge gain by adopting a structure in which the non-volatile memory elements are paired with the read transistor elements, it is recommended to adopt the following constitution.
First, a pair of non-volatile memory elements, as described above, and a pair of read transistor elements, as described above, are provided and the floating gate electrode of one of the non-volatile memory elements is shared by one of the read transistor elements and the floating gate electrode of the other non-volatile memory element is shared by the other read transistor element, and the pair of read transistor elements are connected in series to the transmission means. With this constitution, both of the pair of non-volatile memory elements are programmed in the writing state or in the erasing state. When the pair of non-volatile memory elements are in the writing state, the pair of read transistor elements are off. Here, although the possibility that held charges will be made to leak from the non-volatile memory elements in the writing state for some reason is not zero in probability, even if the held charges leak from one non-volatile memory element, the series path of the read transistors is held cut off, and, hence, the probability that the held charges will leak from both of the pair of non-volatile memory elements is extremely low. This makes it possible to improve the data retention measures and to further reduce the rate of faulty reading.
An example of a circuit form based on this constitution is shown in FIG. 1, in which depression type MIS transistors are vertically stacked as read transistor elements, or the circuit shown in the memory cell section in FIG. 44 is an example in which enhancement type MIS transistors are arranged in series as read transistor elements.
Second, a pair of non-volatile memory elements, as described above, and a pair of read transistor elements, as described above are provided, and the floating gate electrode of one of the non-volatile memory elements is shared by one of the read transistor elements and the floating gate electrode of the other non-volatile memory element is shared by the other read transistor element, and the pair of read transistor elements are connected in parallel to the transmission means. Also in this constitution, in a manner similar to the above example, both of the pair of non-volatile memory elements are programmed into the writing state or into the erasing state. Since in this second example it is assumed that the conductivity type of the read transistor element is different from that of the above example, when the non-volatile memory elements are in the writing state, both of the pair of read transistor elements are on. Here, although the possibility that held charges will leak from the non-volatile memory elements in the writing state due to some cause is not zero in probability, even if the held charges leak from one non-volatile memory element, the parallel path of the read transistor elements is held on, and, hence, the probability that the held charges will leak from both of the pair of non-volatile memory elements is extremely low. This makes it possible to improve the data retention measures and to further reduce the rate of faulty reading.
(4) As a use of the non-volatile memory elements and the read transistor elements, it is thought that redundancy in their structures can be used for recovering faults of the semiconductor integrated circuit. Here, the semiconductor integrated circuit has a plurality of unit information cells, each of which is composed of a pair of non-volatile memory elements and a pair of read transistor elements, and an electric program circuit to the non-volatile memory elements of the plurality of unit information cells, wherein the plurality of unit information cells form the memory circuit for recovery information with respect to a circuit to be recovered. This can improve the reliability of fault recovery.
A fuse program circuit for memorizing recovery information according to the melting state of a fuse element may be provided as another recovery information memory circuit for the circuit to be recovered. It is possible to improve the rate of recovery, in other words, the yield of the semiconductor integrated circuit, by recovering faults detected in the step of a wafer by means of a fuse program circuit and by using the above-mentioned electric program circuit for faults detected after a burn-in test. It is not possible to recover the faults after the burn-in test only by use of the fuse program circuit only the use of the electric program circuit increases the scale of the circuit or the area of the chip as compared with the case where the fuse program circuit is also used with the electric circuit.
The circuit to be recovered may be a memory array in which a DRAM is built. Further, the circuit to be recovered may be a memory array of a DRAM in which a microcomputer is built. Still further, the circuit to be recovered may be a memory array of an SRAM in which a microcomputer is built.
(5) In order to ultimately reduce the rate of faulty reading, it is recommended that a semiconductor integrated circuit be constituted by a plurality of unit information cells, each of which is composed of a pair of non-volatile memory cells and a pair of read transistor elements, wherein a part of the plurality of unit information cells forms a region for holding an error correction code related to the memory information of the remaining unit information cells, a part forms an electric program circuit related to the non-volatile memory elements of the plurality of unit information cells, and a part forms an ECC circuit capable of correcting an error in the read information of the plurality of unit information cells.
In order to ensure an error correction function by the ECC circuit, it is recommended that the electric program circuit has an operation mode of prohibiting writing into the unit information cell, when the ECC circuit is effective.